The present invention relates to an impedance adjusting method for adjusting an impedance and to a semiconductor device comprising an output buffer circuit capable of adjusting an impedance.
In recent years, as the operating speeds of semiconductor devices have become higher, the speeds of signals propagating along signal lines for performing the transmission and reception of the signals between the plurality of semiconductor devices have also become higher. To implement high-speed data transfer, it is necessary to perform impedance matching in a transmission system and suppress the distortion of a transfer waveform due to reflection and the like. To achieve the impedance matching, there has been conventionally adopted a variable-impedance output buffer circuit having an impedance adjustable with respect to the impedance of the transmission system (Patent Documents 1 to 5).
Because the impedance of the output buffer circuit is changed by variations in process conditions, a change in temperature or power source voltage, or the like, there is a case where the impedance shifts from the standard value. In that case also, the control of the impedance of the output buffer circuit is important.
For example, in Japanese Unexamined Patent Publication No. 2001-94048 (Patent Document 1), a semiconductor device comprising an output impedance control circuit capable of performing impedance adjustment with respect to an output buffer circuit is shown.
In FIG. 6 of Patent Document 1, a constant current IZQ is generated by a constant current generating circuit using an external resistor RQ. The number of those of NMOS transistors composing a dummy buffer circuit Ndm which are turned ON is controlled using an U/D counter 224. Likewise, the number of those of PMOS transistors composing a dummy buffer circuit Pdm which are turned ON is controlled using an U/D counter 225. Output data sets D0 to Dn−1 which provide matching between the impedance of the PMOS transistor P2 and that of the dummy buffer circuit Ndm are determined using an operational amplifier OP2. Likewise, output data sets U0 to Um−1 which provide matching between the impedance of the NMOS transistor N2 and that of the dummy buffer circuit Pdm are determined using an operational amplifier OP3. The output data sets D0 to Dn−1 and U0 to Um−1 are given to the output buffer circuit to control the impedance thereof. Because the respective impedances of the PMOS transistor P2 and the NMOS transistor N2 can be changed with the external resistor RQ, the impedance of the output buffer circuit can be arbitrarily set with the external resistor RQ.
In Japanese Unexamined Patent Publication No. Hei 8(1996)-65123 (Patent Document 2), a variable-impedance output buffer is shown. In FIG. 3 of Patent Document 2, the combinations of control signals zqbit0b to zqbit3b which provide matching between the impedances of transistors Q2 to Q5 and the impedance of an external resistor R4 are examined by bringing each of the transistors Q2 to Q5 into conducting/non-conducting states. The control signals zqbit0b to zqbit3b also control transistors Q7 to Q10. The transistors Q2 to Q5 have widths corresponding to ¼ of the respective widths of the transistors Q7 to Q10. Therefore, by changing the external resistor R4, the total impedance of the transistors Q1 to Q5 can be changed and the total impedance of the transistors Q6 to Q10 having a directly proportional relationship therewith can be set.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2001-94048
[Patent Document 2] Japanese Unexamined Patent Publication No. Hei 8(1996)-65123
[Patent Document 3] Japanese Unexamined Patent Publication No. 2005-229177
[Patent Document 4] Japanese Unexamined Patent Publication No. 2005-39549
[Patent Document 5] Japanese Unexamined Patent Publication No. 2002-152032